CHENG WANG. Senior VP Engineering: Architecture, Software, Silicon. Originally from Shanghai, PRC. BSEECS, UC Berkeley. Cheng has led the architecture, silicon implementation and software development for eFPGA over two generations from 180nm-16nm and now neural inferencing. Two years as VLSI designer at Zoran. MSEE, EE PhD UCLA: designed 5 FPGA chips from 90nm to 40nm. 2013 Distinguished PhD Dissertation Award. 2014 ISSCC Lewis Winner Award for Outstanding Paper. Multiple patents at UCLA and Flex Logix.
Flex Logix’s NMAX platform excels at getting high hardware utilization at batch=1, which is critical for edge applications. Most of the new information is in the 2nd half of the slide deck.
NMAX delivers from 1 to 100+TOPS, as you need, at 10x lower cost and 3-5x lower power than existing solutions because we get 50-80% MAC utilization on tough models, meaning we need less silicon area, and we achieve it with 10x less DRAM bandwidth, meaning less DRAM cost and system power.